Implementation of Deep Convolutional Neural Net on a Digital Signal Processor

In this paper I will discuss the feasibility of an implementation of an algorithm containing a Deep Convolutional Neural Network for feature extraction, and softmax regression for feature classification, for the purpose of real-time lane detection on an embedded platform containing a multi-core Digital Signal Processor (DSP). I will explore the merits of using fixed point and floating point arithmetic in the implementation, and provide calculations estimating whether the DSP is capable of real-time operation. While initial calculations suggest that the DSP is capable of real-time operation using floating point and fixed point arithmetic (∼50Hz and ∼60 Hz respectively), problems were encountered using 16-bit fixed point in Q-format, resulting in a failure of the algorithm to properly classify lanes. Future work for this project include exploring the challenges associated with the fixed point implementation, as well completing the migration of the algorithm to multi-core DSP using BLAS libraries.